Mawahib H. Sulieman, Ph.D

Director, Networks & Communication Engineering Program

Assistant Professor

Al Ain Campus

+971 3 7024958

mawahib.sulieman@aau.ac.ae

Biography

Biography

 Mawahib Hussein Sulieman, received the B.Sc. degree in Electrical Engineering from the University of Khartoum, Sudan, in 1996; the M.Sc. degree in Computer and Information Networks from the University of Essex, UK, in 1999; and the Ph.D. degree in Electrical and Computer Engineering from Washington State University, USA, in 2004. From 1999 to 2000, she was a lecturer at the Department of Computer Engineering, University of Gezira, Sudan. In 2004, she joined United Arab Emirates University as Assistant Professor. In 2012, she joined the College of Engineering at Al Ain University, where she is currently the Program Director of the Networks and Communication Engineering Program. Her research interests include nanoelectronics, low-power circuit design, reliability of gates and circuits, and single-Electron Technology.

Education

Ph.D. Electrical and Computer Engineering, Washington State University, USA

M.Sc. Computer and Information Networks, University of Essex, UK

B.Sc. Electrical Engineering, University of Khartoum, Sudan

Research Interests

Nanoelectronics, Low-power circuit design, Reliability of gates and circuits, Single-Electron Technology

Selected Publications

  • M. H. Sulieman et al., “Design and Simulation of a Nanoscale Threshold-Logic Multiplier,” TEM Journal, vol. 8, no. 2, pp. 333–338, May 2019.

  • M. Sulieman and Z. Himat, “On the Design of Nanoscale CMOS Threshold Logic Adders,” Proc. International Multi-conference on Systems, Signals & Devices, March 2018, Tunisia, pp. 1013–1016.

  • Beg, M. Sulieman, V. Beiu, and  W. Ibrahim, “Low-Power Reliable Nano-Adders,” in Nanoelectronic Device Applications Handbook, J. Morris & K. Iniewski (editors), CRC Press , 2017.
  • M. Sulieman, V. Beiu, and W. Ibrahim, “Low-Power and Highly Reliable Logic Gates: Transistor-Level Optimizations," Proc. IEEE Conference on Nanotech. (IEEE-NANO’10), Aug. 2010, Seoul, Korea, pp. 254–257.
  • M. Sulieman, “On the Reliability of Interconnected CMOS Gates Considering MOSFET Threshold-Voltage Variations," Proc. 4th International Conference on Nano Networks (Nano-Net’09), Oct. 2009, Switzerland, Italy, pp. 251–258.
  • M. Sulieman, “Threshold Voltage Variations Effects on the Reliability of Nano-scale CMOS Logic Gates," Proc. IEEE Conference on Nanotech. (IEEE-NANO’09), July 2009, Genoa, Italy, pp. 744–747.
  • W. Ibrahim, V. Beiu, M. Sulieman, “On the Reliability of Majority Gates Full Adders”, IEEE Transactions on Nanotechnology, vol. 7, no. 1, Jan. 2008, pp. 56–67.
  • M. Sulieman, “Reliability of Single-Electron Logic Gates," Proc. 6th WSEAS International Conference on Microelectronics, Nanoelectronics, and Optoelectronics (MINO’07), May 2007, Istanbul, Turkey, pp. 50–53.
  • V. Beiu and M. Sulieman“On Practical Multiplexing Issues,” Proc. IEEE Conf. Nanotech. (IEEE-Nano’06), July 2006, Cincinnati, USA, pp. 310–313.
  • M. Sulieman and V. Beiu, “On Single Electron Technology Full Adders,” IEEE Transactions on Nanotechnology, vol. 4, no. 6, Nov. 2005, pp. 669–680.
  • M. Sulieman, and V. Beiu, “On Single-Electron Technology Full Adders,” Proc. IEEE Conference on Nanotech. (IEEE-NANO’04), 17–19 Aug. 2004, Munich, Germany, pp. 618–621.
  • M. Sulieman, and V. Beiu, “Design and Analysis of SET Circuits: Using MATLAB modules and SIMON,” Proc. IEEE Conference on Nanotech. (IEEE-NANO’04), 17–19 Aug. 2004, Munich, Germany, pp. 317–320.
  • V. Beiu, and M. Sulieman, “Optimal Practical Perceptron Addition – Application to Single-Electron Technology,” Proc. Intl Conf. on VLSI, 21–25 June 2004, Las Vegas, USA, pp. 541–547.
  • M. Sulieman, and V. Beiu, “Characterization of 16-bit Threshold Logic Single-Electron Technology Adder,” Proc. IEEE Intl Symp. Circuits and Systems (ISCAS’04), 23–26 May 2004, Vancouver, Canada, pp. 681–684.
  • M. Sulieman, and V. Beiu, “On the Design of SET adders,” Proc. Nanotech. Conf., 7–11 March 2004, Boston, USA, pp. 169–172.
  • M. Sulieman, and V. Beiu, “Review of Recent Full Adders Implemented in SET,” Proc. IEEE Midwest Symp. on Circuits and Systems (MWSCAS’03), 27–30 Dec. 2003, Cairo, Egypt, pp. 872–875.

Teaching Courses

Circuits Analysis I, Circuits Analysis II, Electronic Circuits, Digital Electronics, Digital Logic Design, Analog Integrated Circuit Design, Special Topics in Electronics, Measurements and Instrumentation, Math and Engineering Applications, Random Signals and Systems

Memberships

Institute of Electrical and Electronics Engineers (IEEE)